.ALIASES
R_RC            RC(1=VOUT 2=N21129 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21447@ANALOG.R.Normal(chips)
C_Cc1           Cc1(1=N22580 2=N21279 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21225@ANALOG.C.Normal(chips)
R_Rs            Rs(1=N26131 2=N21279 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21255@ANALOG.R.Normal(chips)
R_R1            R1(1=N21079 2=N21129 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21015@ANALOG.R.Normal(chips)
C_C1            C1(1=0 2=N21079 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS22713@ANALOG.C.Normal(chips)
R_R2            R2(1=0 2=N21079 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21035@ANALOG.R.Normal(chips)
C_CC3           CC3(1=N26002 2=VOUT ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21293@ANALOG.C.Normal(chips)
R_RE            RE(1=0 2=N22580 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21057@ANALOG.R.Normal(chips)
R_RL            RL(1=0 2=N26002 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21309@ANALOG.R.Normal(chips)
Q_Q1            Q1(c=VOUT b=N21079 e=N22580 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21087@BIPOLAR.Q2N2222.Normal(chips)
V_VCC           VCC(+=N21129 -=0 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21149@SOURCE.VDC.Normal(chips)
V_Vs            Vs(+=N26131 -=0 ) CN @CH4_EX4-5.SCHEMATIC1(sch_1):INS21193@SOURCE.VSIN.Normal(chips)
_    _(vout=VOUT)
.ENDALIASES
