.ALIASES
R_R1            R1(1=N00214 2=VOUT ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS44@ANALOG.R.Normal(chips)
D_D1            D1(1=N00254 2=VOUT ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS69@DIODE.D1N4148.Normal(chips)
D_D2            D2(1=VOUT 2=N00268 ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS85@DIODE.D1N4148.Normal(chips)
V_VS            VS(+=N00214 -=0 ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS578@SOURCE.VSIN.Normal(chips)
V_V1            V1(+=0 -=N00254 ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS110@SOURCE.VDC.Normal(chips)
V_V2            V2(+=N00268 -=0 ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS126@SOURCE.VDC.Normal(chips)
R_RL            RL(1=0 2=VOUT ) CN @CH2_DESIGN-2.SCHEMATIC1(sch_1):INS191@ANALOG.R.Normal(chips)
_    _(vout=VOUT)
.ENDALIASES
