.ALIASES
V_V3            V3(+=N13818 -=0 ) CN @CH2_DESIGN-3.SCHEMATIC1(sch_1):INS13999@SOURCE.VPULSE.Normal(chips)
R_R1            R1(1=0 2=VOUT ) CN @CH2_DESIGN-3.SCHEMATIC1(sch_1):INS14533@ANALOG.R.Normal(chips)
V_V1            V1(+=N13846 -=0 ) CN @CH2_DESIGN-3.SCHEMATIC1(sch_1):INS15513@SOURCE.VDC.Normal(chips)
C_C1            C1(1=N13818 2=VOUT ) CN @CH2_DESIGN-3.SCHEMATIC1(sch_1):INS14096@ANALOG.C.Normal(chips)
D_D1            D1(1=N13846 2=VOUT ) CN @CH2_DESIGN-3.SCHEMATIC1(sch_1):INS13706@DIODE.D1N4148.Normal(chips)
_    _(vout=VOUT)
.ENDALIASES
